1. Fsm1（Simple FSM 1 - asynchronous reset）

状态机可分为两类：

（1）Mealy状态机：输出由当前状态和输入共同决定。输入变化可能立即改变输出。

（2）Moore状态机：输出仅由当前状态决定，与输入无关。输出更稳定，但可能对输入响应较慢。

注意：本题是实现Moore状态机，但其状态转移逻辑是由当前状态与输入共同决定的，该点容易混淆。

首先根据当前状态值得出输出

out = (state == B);

然后根据Fsm1的状态转移图判断出其状态转移逻辑，该部分使用组合逻辑电路实现。状态转移表具体如表1所示：

表1 Fsm1的状态转移表

当前状态	下一状态		输出
当前状态	in = 0	in = 1	输出
B	A	B	1
A	B	A	0

最后对当前状态值进行更新赋值，该部分使用时序逻辑电路实现。

module top_module
#(parameter 	A = 0,parameter 	B = 1
)
(output	out,input 	clk,input 	areset,input 	in
);reg state;reg next_state;// 状态值更新always @(posedge clk, posedge areset) beginif (areset == 1'b1) beginstate <= B;end else beginstate <= next_state;endend// 状态值转换always @(*) begincase (state)A: next_state = (in) ? A : B;B: next_state = (in) ? B : A;endcaseend// 输出赋值assign out = (state==B);
endmodule

2. Fsm1s（Simple FSM 1 - synchronous reset）

注意：由于本题中输出赋值与状态值更新处于同一寄存器中，所以变量 present_state 得充当中间变量，使用阻塞赋值语句，否则会其值的更新会落后一个时钟周期，输出 out 无法被正确赋值。

对于阻塞赋值的中间变量，使用关键字 logic 进行定义。

module top_module(clk, reset, in, out);output 	out; input 	clk;input 	reset;input 	in;reg 	out;parameter A = 0;parameter B = 1;always @(posedge clk) beginlogic present_state;logic next_state;if (reset == 1'b1) begin  present_state	= B;out				<= present_state;end else begin// 状态值转换case (present_state)A: next_state = (in) ? A : B;B: next_state = (in) ? B : A;endcase// 状态值更新present_state = next_state;   // 输出赋值case (present_state)A: out <= 0;B: out <= 1;endcaseendend
endmodule

3. Fsm2（Simple FSM 2 - asynchronous reset）

module top_module
#(parameter 	OFF	= 0,parameter 	ON	= 1
)
(output 	out,input 	clk,input 	areset,input 	j,input 	k
); reg state;reg	next_state;// 状态值更新always @(posedge clk, posedge areset) beginif (areset == 1'b1) beginstate <= OFF;end else beginstate <= next_state;endend// 状态值转换always @(*) begincase (state)OFF:	next_state = (j) ? ON : OFF;ON:		next_state = (k) ? OFF : ON;endcaseend// 输出赋值assign out = (state == ON);
endmodule

4. Fsm2s（Simple FSM 2 - synchronous reset）

module top_module
#(parameter 	OFF	= 0,parameter	ON	= 1 
)
(output 	out,input 	clk,input 	reset,input 	j,input 	k
);reg state;reg next_state;// 状态值更新always @(posedge clk) beginif (reset == 1'b1) beginstate <= OFF;end else beginstate <= next_state;endend// 状态值转换always @(*) begincase (state)OFF:	next_state = (j) ? ON : OFF;ON:		next_state = (k) ? OFF : ON;endcaseend// 输出赋值assign out = (state == ON);
endmodule

5. Fsm3comb（Simple state transitions 3）

module top_module 
#(// 充当数值parameter A = 0, parameter B = 1, parameter C = 2, parameter D = 3
)
(output 			out,output 	[1:0]	next_state,input 			in,input 	[1:0] 	state
);// 状态值变换always @(*) begincase (state)A: next_state = (in) ? B : A;B: next_state = (in) ? B : C;C: next_state = (in) ? D : A;D: next_state = (in) ? B : C;endcaseend// 输出赋值assign out = (state == D);
endmodule

6. Fsm3onehot（Simple one-hot state transitions 3）

module top_module 
#(// 充当序号parameter A = 0, parameter B = 1, parameter C = 2, parameter D = 3
)
(output 			out,output 	[3:0] 	next_state,input 			in,input 	[3:0]	state
);// 输出赋值assign out = state[3];// 状态值变换assign next_state[A] = state[0]&(~in)	| state[2]&(~in);assign next_state[B] = state[0]&in 		| state[1]&in 		| state[3]&in;assign next_state[C] = state[1]&(~in) 	| state[3]&(~in);assign next_state[D] = state[2]&in;
endmodule

7. Fsm3（Simple FSM 3 - asynchronous reset）

module top_module
#(parameter A = 0,parameter B = 1,parameter C = 2,parameter D = 3
)
(output 	reg	out,input 		clk,input 		in,input 		areset
);reg [1:0] sta;reg [1:0] nex_sta;// 状态值更新always @(posedge clk, posedge areset) beginif (areset == 1'b1) beginsta <= A;end else beginsta <= nex_sta;endend// 状态值转换always @(*) begincase (sta)A: nex_sta = (in) ? B : A;B: nex_sta = (in) ? B : C;C: nex_sta = (in) ? D : A;D: nex_sta = (in) ? B : C;endcaseend// 输出赋值assign out = (sta == D);
endmodule

8. Fsm3s（Simple FSM 3 - synchronous reset）

module top_module 
#(parameter A = 0,parameter B = 1,parameter C = 2,parameter D = 3
)
(output 	out,input 	clk,input 	in,input 	reset
); reg [1:0] sta;reg [1:0] nex_sta;// 状态值更新always @(posedge clk) beginif (reset == 1'b1) beginsta <= A;end else beginsta <= nex_sta;endend// 状态值变换always @(*) begincase (sta)A: nex_sta = (in) ? B : A;B: nex_sta = (in) ? B : C;C: nex_sta = (in) ? D : A;D: nex_sta = (in) ? B : C;endcaseend// 输出赋值assign out = (sta == D);
endmodule