verilog简单状态机

1.

always @ (posedge clk or negedge rst_n) beginif (!rst_n)cnt_1ms <= 20'b0;else if (cnt_1ms_en)cnt_1ms <= cnt_1ms + 1'b1;elsecnt_1ms <= 20'd0; 
endalways @ (posedge clk or negedge rst_n) beginif(!rst_n)cur_state <= s1_power_init;else if (EN_POWER_ON==1'b1)cur_state <= s1_power_init;elsecur_state <= next_state;
endalways @ (*) begincase(cur_state)s1_power_init: begin                             // 初始化状态if (st_done==1'b1)next_state = s2_EN_12_power;elsenext_state = s1_power_init;ends2_EN_12_power: begin if (st_done==1'b1)next_state = s3_EN_3_4_power;elsenext_state = s2_EN_12_power;ends3_EN_3_4_power: beginif (st_done==1'b1)next_state = s4_power_done;elsenext_state = s3_EN_3_4_power;ends4_power_done:beginif (st_done==1'b1)next_state = s5_reset_off;elsenext_state = s4_power_done;end  s5_reset_off:beginif (st_done==1'b1)next_state = s6_power_done;elsenext_state = s5_reset_off;end s6_power_done:beginif (st_done==1'b1)next_state = s1_power_init;elsenext_state = s6_power_done;end        default: next_state = s1_power_init;endcase
endalways @ (posedge CLK_25M or negedge wLUTsLoad) beginif(!wLUTsLoad) beginendelse beginst_done <= 1'b0;case (cur_state)s1_power_init:begin                              //初始化if(wEN_POWER_ON==1'b0)begincnt_1ms_en <= 1'b1;if (cnt_1ms<10'd100)st_done <= 1'b0;else beginst_done <= 1'b1;cnt_1ms_en <= 1'b0;endendelse st_done <= 1'b0;ends2_EN_12_power:begincnt_1ms_en <= 1'b1;if (cnt_1ms<10'd100)st_done <= 1'b0;else beginst_done <= 1'b1;cnt_1ms_en <= 1'b0;endends3_EN_3_4_power:begincnt_1ms_en <= 1'b1;if (cnt_1ms<10'd300)st_done <= 1'b0;else beginst_done <= 1'b1;cnt_1ms_en <= 1'b0;endends4_power_done:beginif(PG_1V2&PG_1V8&PG_0V9&PG_3V3&PG_4V&PG_1V&PG_5V)begincnt_1ms_en <= 1'b1;if (cnt_1ms<10'd100)st_done <= 1'b0;else beginst_done <= 1'b1;cnt_1ms_en <= 1'b0;endendelsest_done <= 1'b0;ends5_reset_off:begincnt_1ms_en <= 1'b1;if (cnt_1ms<10'd100)st_done <= 1'b0;else beginst_done <= 1'b1;cnt_1ms_en <= 1'b0;endends6_power_done:beginif(EN_POWER_ON==1'b1) beginst_done <= 1'b1;endelse beginPOWER_ON_OFF <= 1'b1;st_done <= 1'b0;endenddefault:;endcase	end
end