一、模块设计

如若不清楚怎么模块化，请看https://blog.csdn.net/szyugly/article/details/146379170?spm=1001.2014.3001.5501

1.1顶层模块

module top_counter(input  wire       CLOCK_50,    // 50MHz时钟input  wire       KEY0,        // 暂停/继续按键output wire [6:0] HEX3, HEX2, HEX1, HEX0,  // 4位七段数码管output wire [3:0] DIGIT_EN     // 数码管位选
);wire clk_1hz;        // 1Hz时钟
wire clk_scan;       // 扫描时钟(1kHz)
wire pause_pulse;    // 消抖后的暂停信号// 模块实例化
clk_div u_clk_div(.clk_50m(CLOCK_50),.clk_1hz(clk_1hz),.clk_1k(clk_scan)
);debounce u_debounce(.clk(CLOCK_50),.key_in(KEY0),.key_out(pause_pulse)
);time_counter u_time_counter(.clk(clk_1hz),.pause(pause_pulse),.min_ten(min_ten),.min_unit(min_unit),.sec_ten(sec_ten),.sec_unit(sec_unit)
);display u_display(.clk(clk_scan),.min_ten(min_ten),.min_unit(min_unit),.sec_ten(sec_ten),.sec_unit(sec_unit),.seg_data({HEX3, HEX2, HEX1, HEX0}),.digit_en(DIGIT_EN)
);endmodule

1.2计数器模块

module time_counter(input  wire clk,      // 1Hz时钟input  wire pause,    // 暂停信号output reg [3:0] min_ten,  // 分钟十位output reg [3:0] min_unit, // 分钟个位output reg [3:0] sec_ten,  // 秒钟十位output reg [3:0] sec_unit  // 秒钟个位
);reg pause_state;  // 暂停状态寄存器always @(posedge clk) beginif(pause) pause_state <= ~pause_state; // 切换暂停状态
endalways @(posedge clk) beginif(!pause_state) begin  // 非暂停状态// 秒个位计数if(sec_unit == 4'd9) beginsec_unit <= 0;// 秒十位计数if(sec_ten == 4'd5) beginsec_ten <= 0;// 分钟个位计数if(min_unit == 4'd9) beginmin_unit <= 0;// 分钟十位计数if(min_ten == 4'd5) beginmin_ten <= 0;end else beginmin_ten <= min_ten + 1;endend else beginmin_unit <= min_unit + 1;endend else beginsec_ten <= sec_ten + 1;endend else beginsec_unit <= sec_unit + 1;endend
endendmodule

1.3按键消抖模块

module debounce(input  wire clk,      // 50MHz时钟input  wire key_in,   // 原始按键输入output reg  key_out   // 消抖后输出
);reg [19:0] counter;      // 20ms计数器 (50MHz * 0.02s = 1,000,000)
reg key_reg;always @(posedge clk) beginkey_reg <= key_in;    // 同步输入if(key_reg != key_out) begin       // 状态变化counter <= 20'd0;end else if(counter < 20'd1_000_000) begincounter <= counter + 1;end else beginkey_out <= key_reg;           // 稳定后更新输出end
endendmodule

1.4显示驱动模块

module display(input  wire clk,          // 扫描时钟(1kHz)input  wire [3:0] min_ten,input  wire [3:0] min_unit,input  wire [3:0] sec_ten,input  wire [3:0] sec_unit,output reg  [6:0] seg_data,  // 段选信号output reg  [3:0] digit_en    // 位选使能
);reg [1:0] scan_cnt;        // 扫描计数器
reg [3:0] data_temp;       // 当前显示数据// 七段译码表（共阳极）
parameter [6:0] SEG_BCD [0:9] = {7'b1000000, // 07'b1111001, // 17'b0100100, // 27'b0110000, // 37'b0011001, // 47'b0010010, // 57'b0000010, // 67'b1111000, // 77'b0000000, // 87'b0010000  // 9
};always @(posedge clk) beginscan_cnt <= scan_cnt + 1;case(scan_cnt)2'b00: begindigit_en <= 4'b1110;  // 最低位data_temp <= sec_unit;end2'b01: begindigit_en <= 4'b1101;data_temp <= sec_ten;end2'b10: begindigit_en <= 4'b1011;data_temp <= min_unit;end2'b11: begindigit_en <= 4'b0111;  // 最高位data_temp <= min_ten;endendcaseseg_data <= SEG_BCD[data_temp]; // 查表输出
endendmodule

1.5分频模块

module clk_div(input  wire clk_50m,  // 50MHz输入output reg  clk_1hz,  // 1Hz输出output reg  clk_1k    // 1kHz扫描时钟
);// 1Hz分频计数器 (50,000,000分频)
reg [25:0] cnt_1hz;
always @(posedge clk_50m) beginif(cnt_1hz == 26'd49_999_999) begincnt_1hz <= 0;clk_1hz <= ~clk_1hz;end else begincnt_1hz <= cnt_1hz + 1;end
end// 1kHz分频计数器 (50,000分频)
reg [15:0] cnt_1k;
always @(posedge clk_50m) beginif(cnt_1k == 16'd49_999) begincnt_1k <= 0;clk_1k <= ~clk_1k;end else begincnt_1k <= cnt_1k + 1;end
endendmodule

二、效果展示